The Blank Canvas Cape (BCC) is a small (3.4" x 2.15" - standard BeagleBone "Cape" dimensions) board with
a Xilinx Spartan 3A 200Kgate FPGA connected directly to the BeagleBone expansion
connectors. Designed to stack with the BeagleBone according to the method described
in the System Reference Manual, it provides the following features:
Xilinx XC3S200AVQ100 Spartan 3A FPGA with 200kgates, 16 Multipliers and 288kb RAM.
BeagleBone standard I2C ID EEPROM with jumper-selectable address.
28-pin I/O header with 24 pins directly connected to the FPGA, 2 3.3V power pins and 2 GND pins.
JTAG port for FPGA development and debugging.
3x Diagnostic LEDs (2 User defined, 1 Configuration status).
2x User input buttons.
This board was conceived as a general-purpose I/O board with sufficient on-board
logic resources to support experiments in digital audio, Software Defined Radio,
robotics and general experimentation.
Although the BeagleBone Expansion Connectors provide interfaces to the GPMC, LCD/Video,
McASP, SPI, I2C, UARTs, Timers, Interrupts, GPIO and ADC of the AM3xxx SOC, connecting
to all of these is not possible with the FPGA used on this board so the BCC
board only connects to the GPMC bus, SPI0 and I2C2. Access to the other available interfaces
is possible by stacking additional boards.
The GPMC expansion pins are available on connector P8 pins 3-26 and provide 24-bits of I/O
which can be multiplexed for a variety of purposes as shown in the table below:
As configured here, the BCC board supports
multiplexed 16-bit device access with three CS lines for a total address space of
384kB. Because GPMC wait requests are not provided the bus speed will have to be
reduced to accomodate the slowest device access in a single cycle.
At power up the FPGA is set to Configuration Mode  (Master SPI mode) and loads itself
from the on-board SPI Flash memory. By toggling several bits in the I2C2 port expander chip
at bus address 0x38 the FPGA may be set to Configuration Mode  (Slave Serial mode) which
allows the BeagleBone processor to load it via SPI0 at any time. Serial configuration is
quite fast (less than 1 second) in either case and LED301 on the board will
light to indicate a successful configuration.
Altering the content of the on-board SPI flash also uses SPI0. A special temporary
'pass-thru' FPGA design is required which provides a direct connection between SPI0 and
the SPI Flash memory to support programming and verifying the contents of the flash chip.
A bitstream download application which uses kernel I2C and SPIDEV drivers to manage the
process of configuration and programming will be provided for userland setup. Additionally,
a simple C language library of support functions will be available that allows custom applications
to take control of the FPGA board.
A 6-pin JTAG header is provided for external configuration and debug. It
conforms to the Digilent JTAG pinout, but can also be used with Xilinx
download cables if flywires are used. This is handy for testing the FPGA
without the Beagle attached, or for debugging designs using Xilinx's
A 32kbyte I2C EEPROM is available for conformance with the ID protocol described in the
BeagleBone System Reference Manual. Two address select bits are provided with jumper settings
to control the configuration order for stacked boards.
An I2C Port Expander chip is used to control the FPGA configuration process. It resides at
I2C2 Bus Address 0x38. Be sure that there are no other I2C devices in the board stack that
will conflict with this addresss.
The 28-pin I/O header on the right-hand side of the board connects directly to the pins of the
FPGA, providing a completely configurable interface. 24 pins of I/O are provided, alongh with 3.3V
power and ground.
The Xilinx XC3S200A Spartan 3A FPGA on this board is inexpensive and provides sufficient I/O
and logic resources to perform a wide range of interfacing and processing tasks. Simple signal
processing, sequencing and control are certainly possible, as well as some
buffering and reformatting using on-chip RAM.
There are three LEDs are on-board:
LED201 is connected to an I/O pin on the FPGA and can
be used as a visual indicator of internal activity.
LED202 is connected to an I/O pin on the FPGA and can
be used as a visual indicator of internal activity.
LED301 lights when the FPGA has a valid configuration.
There are two user-defined buttons connected to the FPGA which allow real-time human control
of FPGA functions. The buttons are physically aligned with LED201 and LED202 at the top
right corner of the board.
The BeagleBone expansion headers provide one clock from the AM3xxx SOC which is
routed to the FPGA. This board also provides a crystal oscillator to generate a
stable 50MHz clock suitable for high-accuracy timing.
On-board 3.3V and 1.2V LDO regulators derive all the supplies required
from the BeagleBone SYS_5V supply provided on the expansion connector. While the 3.3V
and 1.2V regulators which supply the FPGA I/O and Core voltages are rated for
close to 1A, it is recommended that FPGA designs which require high power are
not considered for this board. Although the Spartan 3A chip used here can
operate at fairly high internal frequencies approaching 200MHz, the practical
limitations of power supply and heat management will constrain the designs
that can safely be realized on this board.
Minimal kernel driver support required for the BCC board includes
I2C2 and SPI0 with SPIDEV, as well as pin muxing to make these interfaces available
on the expansion port. Since the board conforms to the BeagleBone IDPROM
standard it will be recognized by the bootloader and kernel.
Until the IDPROM is set up correctly, the kernel will require some patching
to properly enable the SPI0 bus which is used to configure and communicate with
the FPGA. A short description of the required patches can be found here:
A fragment to enable the SPI0 interface has been submitted for inclusion
and additional fragments to support the GPMC bus are in process here:
A user-space application and access library is available provided which supports
all the features on the board. The application can be used to download FPGA
configuration files, program the SPI Flash memory, control the
programmable clock oscillator and test the SPI control port. The access
library provides a low-level API for control of the I2C and SPI ports,
as well as higher level functions for bitstream download and may be used
to construct complex user-space applications for interaction with the FPGA
design. The source code is available here:
bcc_lib git repository.
Note that a special FPGA bitstream is required to program the on-board
configuration flash memory. The design source is available below in the
Design Documentation section.
Synthesizing an FPGA design requires the Xilinx ISE Webpack which is
a free download from the Xilinx website. This suite of tools includes a
GUI IDE as well as command-line applications that can be run under both
Linux and WinXX. Designs can be created with either Verilog or VHDL. Demo
designs will be provided to showcase the capabilities of the board
and will provide enough detail for starting on custom designs.
I've built an adapter board to allow use of the BCC with Digilent PMODs.
Find out more on the adapter page.