Blank Canvas Cape Spartan 6 version (BCC S6)

Blank Canvas Cape S6

BCC S6 assembled

What is it?

The Blank Canvas Cape - Spartan 6 version (BCC S6) is a small (3.4" x 2.15" - standard BeagleBone "Cape" dimensions) board with a Xilinx Spartan 6 LX9 FPGA connected directly to the BeagleBone expansion connectors. Designed to stack with the BeagleBone according to the method described in the System Reference Manual, it provides the following features:

Design Details

Expansion Connectors

Although the BeagleBone Expansion Connectors provide interfaces to the GPMC, LCD/Video, McASP, SPI, I2C, UARTs, Timers, Interrupts, GPIO and ADC of the AM3xxx SOC, connecting to all of these is not possible with the FPGA used on this board so some expansion signals are unconnected. The interfaces that are used on the BCC S6 include

Detailed Breakdown of Available Connections

PinFunction
3GPMC_AD6/MMC1_DAT6//////GPIO1_6
4GPMC_AD7/MMC1_DAT7//////GPIO1_7
5GPMC_AD2/MMC1_DAT2//////GPIO1_2
6GPMC_AD3/MMC1_DAT3//////GPIO1_3
7GPMC_ADVN_ALE/TIMER4/GPIO2_2
8GPMC_OEN_REN/TIMER7/EMU4/GPIO2_3
9GPMC_BE0N_CLE/TIMER5/GPIO2_5
10GPMC_WEN/TIMER6/GPIO2_4
11GPMC_AD13/LCD_DATA18/MMC1_DAT5/MMC2_DAT1/EQEP2B_IN/PR1_MII0_TXD1/PR1_PRU0_PRU_R30_15/GPIO1_13
12GPMC_AD12/LCD_DATA19/MMC1_DAT4/MMC2_DAT0/EQEP2A_IN/PR1_MII0_TXD2/PR1_PRU0_PRU_R30_14/GPIO1_12
13GPMC_AD9/LCD_DATA22/MMC1_DAT1/MMC2_DAT5/EHRPWM2B/PR1_MII0_CRS//GPIO0_23
14GPMC_AD10/LCD_DATA21/MMC1_DAT2/MMC2_DAT6/EHRPWM2_TRIPZONE_INPUT/PR1_MII0_TXEN//GPIO0_26
15GPMC_AD15/LCD_DATA16/MMC1_DAT7/MMC2_DAT3/EQEP2_STROBE/PR1_ECAP0_ECAP_CAPIN_APWM_O/PR1_PRU0_PRU_R31_15/GPIO1_15
16GPMC_AD14/LCD_DATA17/MMC1_DAT6/MMC2_DAT2/EQEP2_INDEX/PR1_MII0_TXD0/PR1_PRU0_PRU_R31_14/GPIO1_14
17GPMC_AD11/LCD_DATA20/MMC1_DAT3/MMC2_DAT7/EHRPWM2_SYNCI_O/PR1_MII0_TXD3//GPIO0_27
18GPMC_CLK/LCD_MEM_CLK/GPMC_WAIT1/MMC2_CLK/PRT1_MII1_TXEN/MCASP0_FSR/GPIO2_1
19GPMC_AD8/LCD_DATA23/MMC1_DAT0/MMC2_DAT4/EHRPWM2A/PR1_MII_MT0_CLK//GPIO0_22
20GPMC_CSN2/GPMC_BE1N/MMC1_CMD/PR1_EDIO_DATA_IN7/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_13/PR1_PRU1_PRU_R31_13/GPIO1_31
21GPMC_CSN1/GPMC_CLK/MMC1_CLK/PRT1EDIO_DATA_IN6/PRT1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_12/PR1_PRU1_PRU_R31_12/GPIO1_30
22GPMC_AD5/MMC1_DAT5//////GPIO1_5
23GPMC_AD4/MMC1_DAT4//////GPIO1_4
24GPMC_AD1/MMC1_DAT1//////GPIO1_1
25GPMC_AD0/MMC1_DAT0//////GPIO1_0
26gpmc_csn0/gpmc_csn0/gpio1[29]
27lcd_vsync/lcd_vsync/gpmc_a8/pru1_r30_8/pru1_r31_8/gpio2[22]
28lcd_pclk/lcd_pclk/gpmc_a10/pru1_r30_10/pru1_r31_10/gpio2[24]
29lcd_hsync/lcd_hsync/gpmc_a9/pru1_r30_9/pru1_r31_9/gpio2[23]
30lcd_ac_bias_en/lcd_ac_bias_en/gpmc_a11/pru1_r30_11/pru1_r31_11/gpio2[25
39lcd_data6/lcd_data6/gpmc_a6/eQEP2_index/pru1_r30_6/pru1_r31_6/gpio2[12]
40lcd_data7/lcd_data7/gpmc_a7/eQEP2_strobe/pr1_edio_data_out7/pru1_r30_7/pru1_r31_7/gpio2[13]
41lcd_data4/lcd_data4/gpmc_a4/eQEP2A_in/pru1_r30_4/pru1_r31_4/gpio2[10]
42lcd_data5/lcd_data5/gpmc_a5/eQEP2B_in/pru1_r30_5/pru1_r31_5/gpio2[11]
43lcd_data2/lcd_data2/gpmc_a2/ehrpwm2_tripzone_in/pru1_r30_2/pru1_r31_2/gpio2[8]
44lcd_data3/lcd_data3/gpmc_a3/ehrpwm0_synco/pru1_r30_3/pru1_r31_3/gpio2[9]
45lcd_data0/lcd_data0/gpmc_a0/ehrpwm2A/pru1_r30_0/pru1_r31_0/gpio2[6]
46lcd_data1/lcd_data1/gpmc_a1/ehrpwm2B/pru1_r30_1/pru1_r31_1/gpio2[7]

Additional connections on connector P9 are listed below:

PinFunction
10RESET_OUT
11gpmc_wait0/gpmc_wait0/mii2_crs/gpmc_csn4/rmii2_crs_dv/mmc1_sdcd/uart4_rxd/gpio0[30]
12GPMC_BE1N/GMII2_COL/GPMC_CSN6/MMC2_DAT3/GPMC_DIR/PR1_MII1_RXLINK/MCASP0_ACLKR/GPIO1_28
17SPI0_CS0/MMC2_SDWP/I2C1_SCL/EHRPWM0_SYNCI_O/PR1_UART0_TXD/PR1_EDIO_DATA_IN1/PR1_EDIO_DATA_OUT1/GPIO0_5
18SPI0_D1/MMC1_SDWP/I2C1_SDA/EHRPWM0_TRIPZONE_INPUT/PR1_UART0_RXD/PR1_EDIO_DATA_IN0/PR1_EDIO_DATA_OUT0/GPIO0_4
19UART1_RTSN/TIMER5/DCAN0_RX/I2C2_SCL/SPI1_CS1/PR1_UART0_RTS_N/PR1_EDC_LATCH1_IN/GPIO0_13
20UART1_CTSN/TIMER6/DCAN0_TX/I2C2_SDA/SPI1_CS0/PR1_UART0_CTS_N/PR1_EDC_LATCH0_IN/GPIO0_12
21SPI0_D0/UART2_TXD/I2C2_SCL/EHRPWM0B/PR1_UART0_RTS_N/PR1_EDIO_LATCH_IN/EMU3/GPIO0_3
22SPI0_SCLK/UART2_RXD/I2C2_SDA/EHRPWM0A/PR1_UART0_CTS_N/PR1_EDIO_SOF/EMU2/GPIO0_2
24uart1_txd/uart1_txd/mmc2_sdwp/dcan1_rx/i2c1_scl/pru0_r31_16/gpio0[15]
25mcasp0_ahclkx/mcasp0_ahclkx/eQEP0_strobe/mcasp0_axr3/mcasp1_axr1/EMU4/pru0_r30_7/pru0_r31_7/gpio3[21]
26uart1_rxd/uart1_rxd/mmc1_sdwp/dcan1_tx/i2c1_sda/pru1_r30_16/gpio0[14]
27mcasp0_fsr/mcasp0_fsr/eQEP0B_in/mcasp0_axr3/mcasp1_fsx/EMU2/pru0_r30_5/pru0_r31_5/gpio3[19]
28mcasp0_ahclkr/mcasp0_ahclkr/ehrpwm0_synci/mcasp0_axr2/spi1_cs0/ecap2_in_pwm2_out/pru0_r30_3/pru0_r31_3/gpio3[17]
29mcasp0_fsx/mcasp0_fsx/ehrpwm0B/spi1_d0/mmc1_sdcd/pru0_r30_1/pru0_r31_1/gpio3[15]
30mcasp0_axr0/mcasp0_axr0/ehrpwm0_tripzone/spi1_d1/mmc2_sdcd/pru0_r30_2/pru0_r31_2/gpio3[16]
31mcasp0_aclkx/mcasp0_aclkx/ehrpwm0A/spi1_sclk/mmc0_sdcd/pru0_r30_0/pru0_r31_0/gpio3[14]
41EVENT_INTR1/TCLKIN/CLKOUT2/TIMER7/PR1PRU0_PRUR31_16/EMU3/GPIO0_20
42uart3_txd/spi1_cs1/pr1_ecap0_ecap_cap_in_apwm_o/spi1_sclk/mmc0_sdwp/xdma_event_intr2/gpio0[7]

As configured here, the BCC board supports multiplexed 16-bit device access with three CS lines for a total address space of 384kB.

Configuration

The FPGA is set to Configuration Mode [11] (Slave Serial mode) which allows the BeagleBone processor to load it via SPI0 at any time. Serial configuration is quite fast (just a few seconds) and LED301 on the board will light to indicate a successful configuration.

JTAG

A 6-pin JTAG header is provided for external configuration and debug. It conforms to the Digilent JTAG pinout, but can also be used with Xilinx download cables if flywires are used. This is handy for testing the FPGA without the Beagle attached, or for debugging designs using Xilinx's Chipscope application.

ID

A 32kbyte I2C EEPROM is available for conformance with the ID protocol described in the BeagleBone System Reference Manual. Two address select bits are provided with jumper settings to control the configuration order for stacked boards.

Port Expander

An I2C Port Expander chip is used to control the FPGA configuration process. Four additional bits from the port expander are routed to the FPGA for low-speed signaling from the Beaglebone. The port expander resides at I2C2 Bus Address (0x38+board address). Be sure that there are no other I2C devices in the board stack that will conflict with this addresss.

I/O Header

The 40-pin I/O header on the right-hand side of the board connects directly to the pins of the FPGA, providing a completely configurable interface. 32 pins of I/O are provided, alongh with 3.3V and 5V power and ground.

LEDs

There are six LEDs are on-board:

Clocks

The BeagleBone expansion headers provide one clock from the AM3xxx SOC which is routed to the FPGA. This board also provides a crystal oscillator to generate a stable 50MHz clock suitable for high-accuracy timing.

Power

An on-board 3.3V and 1.2V switching regulator derives all the supplies required from the BeagleBone VCC_5V supply provided on the expansion connector. While the 3.3V and 1.2V regulators which supply the FPGA I/O and Core voltages are rated for close to 1A, it is recommended that FPGA designs which require high power are not considered for this board. Although the Spartan 6 chip used here can operate at fairly high internal frequencies approaching 200MHz, the practical limitations of power supply and heat management will constrain the designs that can safely be realized on this board.

Software

Kernel 3.2

Minimal kernel driver support required for the BCC board includes I2C2 and SPI0 with SPIDEV, as well as pin muxing to make these interfaces available on the expansion port. Since the board conforms to the BeagleBone IDPROM standard it will be recognized by the bootloader and kernel.

Until the IDPROM is set up correctly, the kernel will require some patching to properly enable the SPI0 bus which is used to configure and communicate with the FPGA. A short description of the required patches can be found here: multiple-spi-bus-beaglebone.

Kernel 3.8

The EEPROM supports automatic loading of the appropriate DT fragments via the capemgr service. Details on setting up the EEPROM are here: github.com/ka6sox/bcc_software/tree/master/eeprom

A fragment to enable the SPI0 interface has been submitted for inclusion and additional fragments to support the GPMC bus are in process here: github.com/ka6sox/bcc_software

User

A user-space application and access library is available which supports all the features on the board. The application can be used to download FPGA configuration files and test the SPI control port. The access library provides a low-level API for control of the I2C and SPI ports, as well as higher level functions for bitstream download and may be used to construct complex user-space applications for interaction with the FPGA design. The source code is available here: bcc_lib git repository.

FPGA Design

Synthesizing an FPGA design requires the Xilinx ISE Webpack which is a free download from the Xilinx website. This suite of tools includes a GUI IDE as well as command-line applications that can be run under both Linux and WinXX. Designs can be created with either Verilog or VHDL. Demo designs will be provided to showcase the capabilities of the board and will provide enough detail for starting on custom designs.

Design Documentation

Status

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Last Updated
:2014-01-08

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