This is a test prototype for experimenting with Software Defined Radio (SDR). It is composed of several boards that are described in detail elsewhere on this site: Combined with suitable firmware and FPGA design, these boards comprise a receiver capable of capturing 20kHz of signal over 0-20MHz, demodulating it with a variety of formats and driving high-quality audio.

System Architecture

The iceRadio system diagram is shown in Figure 1 below.

iceRadio System Diagram

Figure 1: iceRadio System Diagram


RF input from the antenna first passes thru a 20MHz low-pass anti-aliasing filter (not shown) before entering the RXADC card where it is first amplified and then digitized in an ADC. The maximum input signal allowed without exceeing the range of the ADC puts the 0dBfs point of this system at -10dBm in 50 ohms. The ADC runs at 40MSPS with a resolution of 10 bits, providing approximately 60dB of dynamic range and 20MHz of bandwidth which places the quantization noise floor at about -70dBm.


From the ADC, data passes into the FPGA. This is an iCE5LP4k part which provides 20 4kb RAM blocks and 4 16x16 MAC blocks which are essential for the DSP required for the downconversion. In the FPGA the ADC data is pre-processed to a sample rate appropriate for the MCU. Figure 2 below shows the primary components of the FPGA design.

iceRadio FPGA Diagram

Figure 2: iceRadio FPGA Diagram

Sample Buffer

For diagnostic and analysis, a 1024x11-bit sample buffer is provided which can snapshot the ADC input data as well as the overrange bit and store it in SRAM for analysis by the MCU. This provides the capability to check for overflow and also to generate wide-band signal analysis via DFT to find strong signals within the input passband.

Input Data Formatting

10-bit 40MSPS offset-binary data from the ADC is reformatted to 10 bit two's complement signed for further processing.

Tuning and Real / Complex conversion

10-bit real data passes into a quadrature tuner. Here, a numerically controlled oscillator (NCO) generates the local tuning reference to mix the incoming sampled RF signal down to baseband. In the process the real input signal is converted into complex I and Q. Data precision is maintained at 10-bits.

CIC Decimation

Baseband I and Q is decimated by a factor of 256 in a 4-stage CIC decimator. This structure provides 4 bits of additional resolution due to the integration which takes place. Output is truncated to 16 bits total at a rate of 156.25kSPS.

FIR Decimator

16-bit decimated data at 156.25kSPS is futher decimated by 8 in a FIR decimator. This subsystem provides up to 246 taps of 16-bit FIR coefficients which allows substantial stop-band rejection and fairly narrow transition bands. Corner frequency of the filter is 9kHz but can be easily changed if needed. The output signal is 16 bits at 19.531kSPS, complex.

I2S Master

The 16-bit complex I/Q signal is reformatted as a 16-bit stereo I2S data stream with I on the left channel and Q on the right channel. This signal is sent to both the MCU and to a mux which can select either the raw I / Q signal for the DAC output, or the processed audio returned from the MCU over the I2S data input.

SPI Control Interface

The SPI Control interface provides up to 128 32-bit wide read/write registers which the MCU uses to control the FPGA design and check status. All tuning and configuration of the RF processing takes place thru this interface, as well as triggering the 1k sample buffer and reading back its contents.

Overall FPGA design

The current design which supports only receive operations is using about 37% of the total resources available in the iCE5LP4k. It may be possible to include additional processing functions on the FPGA to reduce the burden on the MCU.


The STM32F303 processor interfaces to the FPGA via SPI and I2S serial ports to control the front end processing and exchange baseband and audio data. Firmware running on the MCU configures the FPGA from a micro-SD card at power up, confirms the presence of the proper design by reading an ID register in the SPI interface and then configures the tuning and mux settings. A background process runs which accepts I2S data from the FPGA, filters it, adjusts gain, applies user-selected demodulation processing and then returns demodulated audio to the FPGA where it is forwarded to the Audio DAC.


The first step in the processing is to further filter the input data. The full 9kHz bandwidth is rarely useful for broadcast and amateur radio signals so a set of real-time selectable 6th-order IIR filters with bandwidths of 8kHz, 6kHz, 4kHz, 2kHz, 1kHz and 500Hz are available.


After decimation and filtering the total signal power can be significantly reduced so an AGC automatically adjusts the signal power to a pre-determined level. The attack and decay time constants of the AGC are separate, allowing for fast attack and slow decay which reduces leading-edge distortion of signals with wide dynamic range such as amateur SSB.


At present the MCU application supports these demodulation types:

These background audio processing algorithms currently require no more than 30% of of the total available CPU cycles. Other demodulation formats may be possible such as various digital modes.

The foreground process on the MCU is either a simple serial command-line interface with simple functions for manipulating the FPGA configuration, tuning setup and background demodulation parameters or a GUI based on a color LCD and rotary encoder.

Future Work

At present the iceRadio system demonstrates basic functionality and provides a good base for improvement. Here's a list, in no particular order, of things to explore in the future:

Design Resources

Return to Radio page.

Last Updated
Comments to:
Eric Brombaugh

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